Themes
Using emerging applications as the driver, CHIMES vision is to demonstrate radical heterogeneous and monolithic integration architectures that enable over a billion transistors per mm2 with an electrical and optical bandwidth density exceeding 500TBps/mm2 at femto-joules/bit energy efficiency while developing simulation, deep co-design, and benchmarking tools and methodologies to drive center metrics and promoting center-to-center collaborations.
To address future systems and application needs, CHIMES is organized into four major research themes—system driven functional integration and aggregation; monolithic 3D (M3D) densification and diversification on silicon platform; ultra-dense heterogeneous interconnect and assembly, and materials behavior, synthesis, metrology, and reliability. Through these research areas, the center aims to enable unprecedented scaling of future systems through the development of new technologies that blurs, merges, and eliminates the chip-package interfaces.
System-Driven Functional Integration & Aggregation
This theme addresses the system-level challenges of monolithic 3D (M3D) and large-scale heterogeneous integration. We attempt to answer the questions of “what to design,” “how to design,” “how to power,” “how to cool,” and “how to test and secure” for such complex emerging integrated systems. The vertical and horizontal scale of these new systems, heterogeneity of the M3D tiers and chiplets, and unprecedented dense connectivity enable a new class of compute, storage, sensing, and communication systems previously not thought possible. Topical areas include:
- System-centric cross-layer benchmarking and path-finding
- Codesign and novel design methodologies for dramatic scale-out and cost reduction
- Novel power distribution schemes for integrated systems
- Thermal modeling and heat extraction at scale and reduced form factor
- Novel test methodologies and side channel security
Researchers
Puneet Gupta, University of California, Los Angeles (Theme Leader)
S.J. Ben Yoo, University of California, Davis
Madhavan Swaminathan, Penn State
Shimeng Yu, Georgia Tech
Inna Partin Vaisband, University of Illinois, Chicago
Subramanian S. Iyer, University of California, Los Angeles
Suresh Sitaraman, Georgia Tech
Zhiting Tian, Cornell University
Krishnendu Chakrabarty, Arizona State University
Michael Taylor, University of Washington
Sung Kyu Lim, Georgia Tech
Monolithic 3D Densification & Diversification on Silicon Platform
To meet the ever-growing compute throughput and energy efficiency requirements for data-intensive applications, monolithic 3D (M3D) integration of multiple tiers of logic and memory devices under back-end-of-line (BEOL) thermal budget is essential. We envision on-chip reconfigurable interconnect, assisted by backside “active” power-delivery-network (PDN) with GaN technologies and embedded heat spreader layers and vias. Researchers in this theme will work to meet the ever-growing compute throughput and energy efficiency requirements for data-intensive applications through multiple tiers of logic and memory devices. Topical areas include:
- Back-end-of-Line (BEOL) low temperature 2D materials synthesis and integration for CMOS logic
- BEOL eNVM array level integration with oxide channel access transistor
- BEOL high-mobility FeFET for reconfigurable interconnect
- GaN integration on silicon for backside active power delivery
- ALD and ALE process for high aspect ration via-formation and ultra-thin channel
- M3D EDA tool and physical design flow and benchmark with thermal awareness
- M3D self-aligned SRAM
Researchers
Shimeng Yu, Georgia Tech (Theme Leader)
Yuji Zhao, Rice University
Inna Partin Vaisband, University of Illinois, Chicago
Tomas Palacios, Massachusetts Institute of Technology
Suman Datta, Georgia Tech
Steven George, University of Colorado
H.S. Philip Wong, Stanford
Volker Sorger, University of Florida
Ultra Dense Heterogeneous Interconnect & Assembly
The objective of this theme is to explore, innovate, and prototype interconnect solutions enabling dramatic performance increases for computing and information processing for both edge and cloud applications. Target innovation paradigms include:
- High parallelism ICs including heterogeneous integration & fine-pitched metallic ICs, and multi-chiplet packaging with active inter-connections
- Thermal cooling and power delivery via in-package cooling & thermal management, and advanced power delivery with embedded IVR and inductors, micro-coolers, thermal materials at wafer-scale
- Embedded wireless ICs feeding integrated antenna arrays featuring hardware co-design & co-integration for RF signal I/O, communication and fan-out
- Photonic ICs for inter- and intra chiplet communication targeting in-package optics, photonic ICs for chiplet-chiplet and accelerator-chiplet communication, and optical TSV including optic-to-mmWave conversions
- Reconfigurable circuits featuring electronic-photonic neural network accelerator
- Next-generation active and passive optoelectronic components
- Fine-pitched 3D stacking
Topical areas include:
- Fine pitch via-enabled interconnect parallelism and self-alignment die assembly
- High heat flux removal for multi-functional passive and dynamic operation
- Vertical 3D tiers for high-fanout and wireless I/O interconnectivity
- Ultrahigh-speed serial optical signaling between optical chiplets
- Reconfigurable optoelectronic circuits for front-end sensor pre-processing and AI hardware
- Power delivery and cooling
- Optical TSV for any tier communication to M3D
Researchers
Volker Sorger, University of Florida (Theme Leader)
Muhannad Bakir, Georgia Tech
Andrew Kummel, University of California, San Diego
Madhavan Swaminathan, Penn State
Satish Kumar, Georgia Tech
Suresh Sitaraman, Georgia Tech
Inna Partin Vaisband, University of Illinois, Chicago
Tomas Palacios, Massachusetts Institute of Technology
S.J. Ben Yoo, University of California, Davis
Shimeng Yu, Georgia Tech
Puneet Gupta, University of California, Los Angeles
Michal Lipson, Columbia University
Muhannad Bakir, Georgia Tech
Subramanian S. Iyer, University of California, Los Angeles
H.S. Philip Wong, Stanford
Materials Behavior, Synthesis, Metrology, & Reliability
This theme will focus on new materials needed for radically new monolithic and heterogenous integration strategies. This requires new principles and methods for materials design across length scales, from tenths of nanometers to micrometers, as well as new approaches to the characterization of properties and reliability of materials in integrated structures. In this theme, machine learning (ML) enhanced material property prediction for materials design as well as ML for more accurate and efficient reliability assessment will be developed in concert with studies focused on materials synthesis and integration.
New materials for thermal management will include thermal interface materials with high through-thickness thermal conductivity and low stiffness, heat spreaders and thermal vias made using diamond for 3D conduction and 2D hexagonal BN for 2D conduction, and low-stiffness thermal isolation materials based on polymer hydrogels. Methods for interface nano-structuring and atomic interdiffusion to lower the thermal resistance of interfaces for use in M3D and HI architectures will be investigated, as well as methods for infilling of heat spreaders between densely interconnected stacked chips. Ultra-low-k/low-loss- dielectric materials with optimized mechanical and thermal properties will be. Advanced techniques for atomic layer deposition and atomic layer etching will be employed, a bottom-up method for formation of high-aspect-ratio interconnects.
Researchers
Carl V. Thompson, Massachusetts Institute of Technology (Theme Leader)
Satish Kumar, Georgia Tech
Zhiting Tian, Cornell
Yuji Zhao, Rice University
Ximin He, University of California, Los Angeles
Subramanian S. Iyer, University of California, Los Angeles
Madhavan Swaminathan, Penn State
Steven George, University of Colorado
Suman Datta, Georgia Tech
Andrew C. Kummel, University of California, San Diego
Muhannad Bakir, Georgia Tech
